ESP32 Ethernet - Change ClkOut Pin

Hello,

I am trying to modify the phy_lan8720.c file so that the emac clock out will be on GPIO17 but any changes to this file seem to have no effect when the project is compiled and the eth_driver.init() function is called.

The output during compilation shows the phy_lan8720.c as an argument.

[info] Compiling module: espressif.esp32net.esp32eth @ C:\Users\mc\zerynth2\dist\r2.2.0\libs\official\espressif\esp32net\esp32eth.py

[warning] Following CBuild C:/Users/mc/zerynth2/dist/r2.2.0/libs/official/espressif/esp32net/csrc/cbuild.json

[warning] ESP32_ETH_PHY_LAN8720 {‘inc’: [’.’], ‘src’: [‘eth_phy/phy_common.c’, ‘eth_phy/phy_lan8720.c’], ‘defs’: []} set() {‘LAYOUT’: [‘olimex_esp32gateway’], ‘CDEFS’: [‘ESP32_VHAL’, ‘ESP32_ETH_PHY_LAN8720’, ‘HAS_BUILTIN_MBEDTLS’], ‘CFG’: {‘ESP32_VHAL’: 1, ‘HAS_BUILTIN_MBEDTLS’: 1, ‘ESP32_ETH_PHY_LAN8720’: 1}, ‘BOARD’: ‘olimex_esp32gateway’}

[warning] added C:\Users\mc\zerynth2\dist\r2.2.0\libs\official\espressif\esp32net\csrc

The default emac clock seems to be GPIO_0 as input but having some communication issues using that method.

Thks.
Mark

Hi @bigmc777!

I was experiencing the same problem: I found that the following changes on the driver files solved that:
wifi_ifc.c , line 387 -> cfg.clock_mode = ETH_CLOCK_GPIO17_OUT;
phy_common.c , line 38 -> gpio_set_direction(17, GPIO_MODE_INPUT);
phy_lan8720.c , line 122 -> .clock_mode = ETH_CLOCK_GPIO17_OUT,

Apparently the Olimex Gateway Rev.E is missing the oscillator present in Revs B and C (don’t know if it is in D), so there is why this is a needed change in configuration.

Hello,

Thks for your response. I was considering not using the zerynth anymore due to lack of support but your response seemed to do the trick. I needed to modify the wifi_ifc.c and phy_common.c files in order to get the clock out of gpio17. Thanks for your help. A product is only as good as the support behind it.

Mark

Hi @bigmc777
We are very sorry for the delay in response and support, We can assure you that the support will be much better on the community forums.
And please let me know if you need further technical help in your development activities.

Karim Hamdy
Zerynth development team.

Thanks @NicolasDiaz for sharing this piece of information.:smile:

Hello,

I have done some further testing on our new boards with the GPIO17 clock out and run into the following problem. The driver.init() call works with no errors (on the scope this is when the clock is generated) and then I call the eth.link() at which point the LED link light begins to flash like it is negotiating for a few transactions and then it just starts flashing rapidly and the connection is lost on zerynth. I wanted to know if the eth module in zerynth is compatible with the LAN8720 chip or do i have to define somewhere in the zerynth native C files that I am using the 8720 chip? I see a lot of posts and info for ESP-IDF on setting configurations online.

Thks.
Mark